Multi-Stage Muxing Scheme for Generating PRBS at a Higher Bit Rate

The Targeted Problem

There are needs for a PRBS of very high bit rate while the technology of digital circuitry might only allows the hardware to generate a PRBS at a lower bit rate. This problem is often solved through the usage of several multiplexers (MUXs or muxs) by combining 2M parallel signals (at lower bit rate) into a single sequence at the desired high bit rate. An overall 2M:1 muxing can be realized in multiple caccaded stages. For example, an overall 64:1 muxing may by realized with a muxing stage of 64:16 followed by another of 16:1. The two muxing stages can be written as (64:16:1) in short. Alternatively, the same overall muxing result of 64:1 may also achieved by schemes like (64:8:4:1), (64:16:4:2:1) and etc. All input signals are presumably implemented by identical LFSRs with N bits length. Then, depending on the selected multi-stage muxing scheme, this applet helps the designer of the pattern generator (PG) to determine how each of the input shift registers is properly seeded such that the eventual serial output signal is a m-sequence running at the high bit rate.

The 2M parallel inputs need not be implemented with 2M identical LFSRs, which is too expensive. A fast parallel generator may be a good alternative.

Brief User' Guide

  • The user should have a general knowledge of how an LFSR works, otherwise, visit LFSR first
  • A desired (2N-1) PRBS at the output if it would be generated by a single LFSR is determined by three factors: (1) Number of bits in the shift register, N, (2) Feedback coefficients, and (3) seeding bits of the register.
  • The user set the value N in the assigned ttext-field
  • A click on the button "Get coefficients" will cause the applet to generate one set of non-zero feedback coefficients in the corresponding text-field. However, the user can modify these coefficient to a differenet set
  • The user should enter N binary values, separated by space, in the text-field named "Single LFSR seed vector"
  • The text-fields labeled "Input bit rate" and "Output bit rate" prompt for the bit rates at inputs and the output, in Gb/s
  • A click on the button "Calc Mux Ratio" causes the applet to (i) compute an appropriate number, 2M, in the text-field labeled "Overall muxing ratio" for the overall required muxing ratio (64 for example), and (ii) Suggest a cascaded muxing scheme (such as "64:8:1"). At this point, the overall ratio and the cascaded muxing scheme can still be modified by the user to a different set of values.
  • A click on the button labeled "Draw Muxing Scheme" will cause the last selected muxing scheme to be drawn in a simplified circuit diagram
  • Next, the user should provide the number of bits needed in the simulation in the appropriate text-field, then click the "Simulate" button
  • The computed seeding values for the parallel input registers are listed in the first text-area, while the higher-rate output sequence is listed in the second text-area
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